Method for manufacturing static random access memory device

ABSTRACT

In a method of manufacturing an SRAM device, an insulating layer is formed over a substrate. First dummy patterns are formed over the insulating layer. Sidewall spacer layers, as second dummy patterns, are formed on sidewalls of the first dummy patterns. The first dummy patterns are removed, thereby leaving the second dummy patterns over the insulating layer. After removing the first dummy patterns, the second dummy patterns are divided. A mask layer is formed over the insulating layer and between the divided second dummy patterns. After forming the mask layer, the divided second dummy patterns are removed, thereby forming a hard mask layer having openings that correspond to the patterned second dummy patterns. The insulating layer is formed by using the hard mask layer as an etching mask, thereby forming via openings in the insulating layer. A conductive material is filled in the via openings, thereby forming contact bars.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.15/811,426, filed on Nov. 13, 2017, now U.S. Pat. No. 10,763,266, whichis a continuation of U.S. patent application Ser. No. 14/958,592, filedon Dec. 3, 2015, now U.S. Pat. No. 9,842,843, the entire disclosures ofeach of which are incorporated herein by reference.

TECHNICAL FIELD

The disclosure relates to a semiconductor device, and more particularlyto a method for manufacturing an SRAM (Static Random Access Memory)device having fin field effect transistor (Fin FET) devices.

BACKGROUND

As the semiconductor industry has progressed into nanometer technologyprocess nodes in pursuit of higher device density, higher performance,lower power consumption and lower costs, challenges from bothfabrication and design issues have resulted in the development ofthree-dimensional designs, such as a fin field effect transistor (FinFET). In a Fin FET device, it is possible to utilize additionalsidewalls and to suppress a short channel effect.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is best understood from the following detaileddescription when read with the accompanying figures. It is emphasizedthat, in accordance with the standard practice in the industry, variousfeatures are not drawn to scale and are used for illustration purposesonly. In fact, the dimensions of the various features may be arbitrarilyincreased or reduced for clarity of discussion.

FIG. 1 is an exemplary circuit diagram of an SRAM unit cell.

FIG. 2 is an exemplary layout of an SRAM unit cell according to oneembodiment of the present disclosure.

FIG. 3 is an exemplary arrangement of plural SRAM unit cells.

FIG. 4 is an exemplary arrangement of plural SRAM unit cells accordingto one embodiment of the present disclosure.

FIG. 5A shows an exemplary perspective view of a fin field effecttransistor.

FIG. 5B shows an exemplary cross sectional view along line X1-X1 of FIG.2.

FIG. 5C is an exemplary cross sectional view illustrating verticallayers.

FIGS. 6 and 7 are exemplary layouts of an SRAM unit cell according toone embodiment of the present disclosure.

FIGS. 8A-12C show exemplary sequential processes for manufacturing finstructures for an SRAM device according to one embodiment of the presentdisclosure.

FIGS. 13-17B show exemplary sequential processes for manufacturing gatestructures for an SRAM device according to one embodiment of the presentdisclosure.

FIGS. 18-28B show exemplary sequential processes for manufacturingcontact bar structures for an SRAM device according to one embodiment ofthe present disclosure.

DETAILED DESCRIPTION

It is to be understood that the following disclosure provides manydifferent embodiments, or examples, for implementing different featuresof the invention. Specific embodiments or examples of components andarrangements are described below to simplify the present disclosure.These are, of course, merely examples and are not intended to belimiting. For example, dimensions of elements are not limited to thedisclosed range or values, but may depend upon process conditions and/ordesired properties of the device. Moreover, the formation of a firstfeature over or on a second feature in the description that follows mayinclude embodiments in which the first and second features are formed indirect contact, and may also include embodiments in which additionalfeatures may be formed interposing the first and second features, suchthat the first and second features may not be in direct contact. Variousfeatures may be arbitrarily drawn in different scales for simplicity andclarity.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly. In addition, the term“made of” may mean either “comprising” or “consisting of.”

Further, the layout structures shown in the present disclosure aredesign layouts and do not necessarily show exact physical structuresfabricated as a semiconductor device.

FIG. 1 is an exemplary circuit diagram of an SRAM unit cell. An SRAMunit cell includes two cross-coupled inverters having a data storagenode and a complementary data storage node. The output of the firstinverter is coupled to the input of the second inverter, and the outputof the second inverter is coupled to the input of the first inverter.The SRAM further includes a first pass-gate FET device PG1 coupled tothe output of the first inverter and the input of the second inverterand a second pass-gate FET device PG2 coupled to the output of thesecond inverter and the input of the first inverter. Gates of the firstand second pass-gate FET devices are coupled to a word line WL, asource/drain of the first pass-gate FET device PG1 is coupled to a firstbit line BL, and a source/drain of the second pass-gate FET device PG2is coupled to a second bit line BLB, which is the complement of thefirst bit line BL. In the present disclosure, a source and a drain of anFET device may be interchangeably used.

The first inverter includes a first first-conductive-type FET device PU1and a first second-conductive-type FET device PD1. The second inverterincludes a second first-conductive-type FET device PU2 and a secondsecond-conductive-type FET device PD2. The first pass-gate device PG1and the second pass-gate device PG2 are second-conductive type devices.In the embodiment, the first conductive type is a P-type and the secondconductive type is an N-type. Of course, it is possible in anotherembodiment that the first conductive type is an N-type and the secondconductive type is a P-type, and in such a case the remaining elementsin the SRAM are appropriately modified according to the common knowledgein the art.

The SRAM further includes a first P-type well PW1, a second P-type wellPW2 and an N-type well NW. As shown in FIG. 1, the first pass-gatedevice PG1 (N-type) and the first N-type FET device PD1 are disposedwithin the first P-type well PW1, the second pass-gate FET device PG2(N-type) and the second N-type FET device PD2 are disposed within thesecond P-type well PW2, and the first P-type FET device PU1 and thesecond P-type FET device PU2 are disposed within the N-type well NW.

FIG. 2 is an exemplary layout of an SRAM unit cell according to oneembodiment of the present disclosure. In FIG. 2, only some oflower-layer elements are illustrated.

The SRAM unit cell is defined by a cell boundary CELB, and includesfirst to fourth fin structures F1, F2, F3 and F4, each extending in theY (column) direction and arranged in the X (row) direction. The four finstructures F1, F3, F4 and F2 are arranged in the X direction in thisorder. The cell boundary CELB has a bottom side extending in the Xdirection, a top side extending in the X direction and opposing to thebottom side, a left side extending in the Y direction and a right sideextending in the Y direction and opposing to the left side.

The SRAM unit cell includes six transistors. The first pass-gate devicePG1 is a fin field effect transistor (Fin FET) (PG1) formed by a firstgate electrode GA1 and the first fin structure F1. The first N-type FETdevice PD1 is a Fin FET formed by a second gate electrode GA2 and thefirst fin structure F1. The first P-type FET device PU1 is a Fin FETformed by the second gate electrode GA2 and the third fin structure F3.The second pass-gate FET device PG2 is a Fin FET formed by a third gateelectrode GA3 and the second fin structure F2. The second N-type FETdevice PD2 is a Fin FET formed by a fourth gate electrode GA4 and thesecond fin structure F2. The second P-type FET device PU2 is a Fin FETformed by the fourth gate electrode GA4 and the fourth fin structure F4.Each of the six Fin FETs in the SRAM unit cell includes only one activefin structure functioning as a channel and source/drain.

The SRAM unit cell of the embodiment further includes a first contactbar CB1 that is formed over the source of the Fin FET PD1 including asource/drain (S/D) epitaxial layer formed over the first fin structure,and a second contact bar CB2 that is formed over the source of the FinFET PD2 including an S/D epitaxial layer formed over the second finstructure. The first and second contact bars CB1 and CB2 areelectrically connected to a first power supply line, for example, Vss.The S/D epitaxial layer is made of one or more layers of SiP, SiC, SiCP,Si, Ge, or a Group III-V material. The contact bars may be made of oneor more layer of Cu, W, Al, AlCu, TiN, TiW, Ti, Co, Ni, TaN, Ta, orother refractory metal, or combinations thereof.

As shown in FIG. 2, the first and second fin structures F1 and F2 extendin the Y direction from a bottom side of the cell boundary CELB and atop side of the cell boundary CELB opposite to the bottom side. Thethird fin structure F3 extends in the Y direction from the bottom sideof the cell boundary CELB and is shorter than the first and second finstructures. The fourth fin structure F4 extends in the Y direction fromthe top side of the cell boundary CELB and is shorter than the first andsecond fin structures.

The SRAM unit cell further includes third to eighth contact bars(contact plugs) CB3-CB8. The third contact bar CB3 connects a drain ofthe FinFET PG1 and a drain of the Fin FET PD1 to a drain of the Fin FETPU1, and electrically connected to the word line. The fourth contact barCB4 connects a drain of the FinFET PG2 and a drain of the Fin FET PD2 toa drain of the Fin FET PU2, and electrically connected to the word line.The fifth contact bar CB5 is disposed over a source of the Fin FET PG1,and electrically connected to a bit line. The sixth contact bar CB6 isdisposed over a source of the Fin FET PU1, and electrically connected toa second power supply line, for example, Vdd. The seventh contact barCB7 is disposed over a source of the Fin FET PU2, and electricallyconnected to the second power supply line. The eighth contact bar CB8 isdisposed over a source of the Fin FET PG2, and electrically connected toa complementary bit line.

The SRAM includes a plurality of SRAM unit cells arranged in the X (row)and Y (column) directions. FIG. 3 shows an exemplary layout of four SRAMunit cells, first to fourth SRAM unit cells, SR1, SR2, SR3 and SR4. Thefirst SRAM SR1 has, for example, the layout structures shown by FIG. 2.The second SRAM SR2 has a layout which is a horizontally flipped layoutof the first SRAM SR1 with respect to an axis parallel to the Ydirection. The third SRAM SR3 has a layout which is a vertically flippedlayout of the first SRAM SR1 with respect to an axis parallel to the Xdirection. The fourth SRAM SR4 has a layout which is a horizontallyflipped layout of the third SRAM SR3 with respect to an axis parallel tothe Y direction. Along the column direction (Y), plural first SRAMs SR1and plural third SRAMs SR3 are alternatively arranged.

FIG. 4 shows an SRAM array showing 3 rows and 2 columns. Each SRAM unitcell has the layout structure of FIG. 2 and its flipped structures asset forth above.

As shown in FIG. 4, the first contact bar CB1 is located on a first side(left side) of the cell boundary CELB of one SRAM unit cell (e.g., SR1)and electrically connects the source of the Fin FET PD1 in the SRAM unitcell and the sources of the Fin FETs PD1 in the adjacent SRAM unit cells(e.g. SR2-SR4). The second contact bar CB2 is located on a right sideand an upper side of the cell boundary CELB of one SRAM unit cell (e.g.,SR1) and electrically connects the source of the Fin FET PD2 in the SRAMunit cell and the sources of the Fin FETs PD2 in the adjacent SRAM unitcells (e.g., SR2-SR4). The first and second contact bars CB1, CB2 areshared by the adjacent four SRAM unit cells.

The fifth contact bar CB5 is located on the upper side of the cellboundary in one SRAM unit cell (e.g., SR1) and connects the source ofthe Fin FET PG2 in the SRAM unit cell and the source of the Fin FET PG2in the adjacent SRAM unit cell in the Y direction. The sixth contact barCB6 is located on the lower side of the cell boundary in one SRAM unitcell (e.g., SR1) and connects the source of the Fin FET PU1 in the SRAMunit cell and the source of the Fin FET PU1 in the adjacent SRAM unitcell in the Y direction. The seventh contact bar CB7 is located on theupper side of the cell boundary in one SRAM unit cell (e.g., SR1) andconnects the source of the Fin FET PU2 in the SRAM unit cell and thesource of the Fin FET PU2 in the adjacent SRAM unit cell in the Ydirection. The eighth contact bar CB8 is located on the lower side ofthe cell boundary in one SRAM unit cell (e.g., SR1) and connects thesource of the Fin FET PG2 and the source of the Fin FET PG2 in theadjacent SRAM unit cell in the Y direction.

In the alternative, it can be said that the first and second contactbars CB1 and CB2 are disposed at corners where four adjacent SRAM unitcells SR1-SR4 gather, and are shared by four SRAM unit cells, and thefifth to eighth contact bars CB5-CB8 are shared by adjacent SRAM unitcells in the Y direction.

FIG. 5A shows an exemplary perspective view of a Fin FET. The Fin FET 1include, among other features, a substrate 10, a fin structure 20, agate dielectric 30 and a gate electrode 40. In this embodiment, thesubstrate 10 is a silicon substrate. Alternatively, the substrate 10 maycomprise another elementary semiconductor, such as germanium; a compoundsemiconductor including Group IV-IV compound semiconductors such as SiCand SiGe, Group III-V compound semiconductors such as GaAs, GaP, GaN,InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP, and/orGaInAsP; or combinations thereof. The fin structure 20 is disposed overthe substrate. The fin structure 20 may be made of the same material asthe substrate 10 and may continuously extend from the substrate 10. Inthis embodiment, the fin structure is made of Si. The silicon layer ofthe fin structure 20 may be intrinsic, or appropriately doped with ann-type impurity or a p-type impurity.

The lower part of the fin structure 20 under the gate electrode 40 isreferred to as a well region, and the upper part of the fin structure 20is referred to as a channel region. Under the gate electrode 40, thewell region is embedded in the isolation insulating layer 50, and thechannel region protrudes from the isolation insulating layer 50. Spacesbetween the fin structures 20 and/or a space between one fin structureand another element formed over the substrate 10 are filled by anisolation insulating layer 50 (or so-called a “shallow-trench-isolation(STI)” layer) including an insulating material. The insulating materialfor the isolation insulating layer 50 may include silicon oxide, siliconnitride, silicon oxynitride (SiON), SiOCN, fluorine-doped silicate glass(FSG), or a low-k dielectric material.

The channel region protruding from the isolation insulating layer 50 iscovered by a gate dielectric layer 30, and the gate dielectric layer 30is further covered by a gate electrode 40. Part of the channel regionnot covered by the gate electrode 40 functions as a source and/or drainof the MOS FET.

In certain embodiments, the gate dielectric layer 30 includes adielectric material, such as silicon oxide, silicon nitride, or high-kdielectric material, other suitable dielectric material, and/orcombinations thereof. Examples of high-k dielectric material includeHfO₂, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminumoxide, titanium oxide, hafnium dioxide-alumina (HfO₂—Al₂O₃) alloy, othersuitable high-k dielectric materials, and/or combinations thereof.

The gate electrode 40 includes any suitable material, such aspolysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt,molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN,TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials,and/or combinations thereof. The gate structure may be formed using agate-last or replacement gate methodology.

In some embodiments, one or more work function adjustment layers (notshown) may be interposed between the gate dielectric layer and the gateelectrode. The work function adjustment layers are made of a conductivematerial such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al,TiAl, HfTi, TiSi, TaSi, NiSi, PtSi or TiAlC, or any other suitablematerials, or a multilayer of two or more of these materials. For then-channel Fin FET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi,TiSi and TaSi, or any other suitable materials, is used as the workfunction adjustment layer, and for the p-channel Fin FET, one or more ofTiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC and Co, or any other suitablematerials, is used as the work function adjustment layer. The workfunction adjustment layer may be formed separately for the n-channel FinFET and the p-channel Fin FET which may use different metal layers.

Source and drain regions are also formed in the fin structure 20 notcovered by the gate electrode 40, by appropriately doping impurities inthe source and drain regions or epitaxially growing appropriatematerial. An alloy of Si or Ge and a metal such as Co, Ni, W, Ti or Tamay be formed on the source and drain regions.

FIG. 5B shows an exemplary cross sectional view along line X1-X1 of FIG.2. An epitaxial S/D layer 25 is formed on each of the fin structures F1,F4 and F2. Further, the second contact bar CB2 is formed on the S/Dlayers of the second fin structure F2. The fifth and seventh contactbars CB5 and CB7 are formed on the first fin structure F1 and the fourthfin structure F4, respectively.

FIG. 5C shows an exemplary cross sectional view illustrating a verticallayer arrangement of the SRAM. FIG. 5C does not necessarily show aspecific cross section of the SRAM unit cell described with FIGS. 2-4.

In the substrate layer the fin structures and source/drain structuresare disposed. In the gate layer, gate structures including gateelectrodes and gate dielectric layers are disposed. The gate contactlayer is located above the gate layer. The contact bars are located inthe contact bar layer extending from the gate layer to the gate contactlayer. In the first via layer located over the gate contact layer andthe contact bar layer, first vias are disposed. In the first metallayer, the first metal wirings are disposed. In the second via layer,the second vias are disposed. In the second metal layer level, secondmetal wirings are is disposed.

FIGS. 6 and 7 show an exemplary upper-layer layout of an SRAM unit cellaccording to the embodiment of the present disclosure.

As shown in FIG. 6, the SRAM unit cell further includes first to fourthgate contacts GC1-GC4. The first gate contact GC1 is disposed on thefirst gate electrode GA1, and a second gate contact GC2 is disposed onthe third gate electrode GA3. The third gate contact GC3 is disposedover the fourth gate electrode GA4 and the third contact bar CB3 andelectrically connects the fourth gate electrode GC4 and the thirdcontact bar CB3. The fourth gate contact GC4 is disposed over the thirdgate electrode GA3 and the fourth contact bar CB4 and electricallyconnects the third gate electrode GA3 and the fourth contact bar CB4. Asshown in FIG. 6, the first and second gate contacts GC1 and GC2 arelocated on the cell boundary CELB and shared by adjacent SRAM unitcells.

The SRAM unit cell further includes first to eighth vias V1-V8. Thefirst via V1 is disposed over the first gate contact GC1, and the secondvia V2 is disposed over the second gate contact GC2. The third via V3 isdisposed over the first contact bar CB1, and the fourth via V4 isdisposed over the second contact bar CB2. The fifth via V5 is disposedover the fifth contact bar CB5, the sixth via V6 is disposed over thesixth contact bar CB6, the seventh via V7 is disposed over the seventhcontact bar CB7, and the eighth via V8 is disposed over the eighthcontact bar CB8. As shown in FIG. 6, the vias V1-V8 are located on thecell boundary CELB and shared by adjacent SRAM unit cells. The viasV1-V8 are formed in the first via layer shown in FIG. 5C.

FIG. 6 also shows the bit line BL, the second power supply line VDD andthe complementary bit line BLB, which extend in the Y direction overplural SRAM unit cells. The bit line BL is electrically connected to thesource of the Fin FET PG1 (formed on the first fin structure F1) throughthe fifth via V5 and the fifth contact bar CB5, and the complementarybit line BLB is electrically connected to the source of the Fin FET PG2(formed on the second fin structure F2) through the eighth via V8 andthe eighth contact bar CB8. The second power supply line VDD iselectrically connected to the source of the Fin FET PU1 (formed on thethird fin structure F3) and the source of the Fin FET PU2 (formed on thefourth fin structure F4) through the sixth and seventh vias V6 and V7and the sixth and seventh contact bars CB6 and CB7, respectively.

In addition, first to fourth local plates LP1-LP4 are provided. Thefirst local plate LP1 is electrically connected to the first gateelectrode through the first via V1 and the first gate contact GC1, andthe second local plate LP2 is electrically connected to the third gateelectrode GC3 through the second via V2 and the second gate contact GC2.The third local plate LP3 is electrically connected to the source of theFin FET PD1 through the third via V3 and the first contact bar CB1, andthe fourth local plate LP4 is electrically connected to the source ofthe Fin FET PD2 through the fourth via V4 and the second contact barCB2. The bit line BL, the complementary bit line BLB, the second powersupply line VDD and the first to fourth local plates are formed in thefirst metal layer shown in FIG. 5C.

FIG. 7 shows an exemplary upper-layer layout of an SRAM unit cell. Aword line WL extending in the X direction is provided and iselectrically connected to the first and second local plates LP1 and LP2through a first upper via VA1 and a second upper via VA2. Two firstpower supply lines VS1 and VS2 extending in the X direction are alsoprovided, and are connected to the third fourth local plates LP3 and LP4through a third upper via VA3 and a fourth upper via VA4, respectively.

As shown in FIG. 7, the first and second upper vias VA1 and VA2 arelocated on the cell boundary CELB and shared by adjacent SRAM unitcells, and the third and fourth upper vias VA3 and VA4 are located atthe corner of the cell boundary CELB, and are shared by four adjacentSRAM unit cells. The upper vias VA1-VA4 are formed in the second vialayer and the word lines WL and the first power supply lines VS1 and VS2are formed in the second metal layer, as shown in FIG. 5C.

The vias and metal layers are made of one or more layers of Cu, W, Al,AlCu, TiN, TiW, Ti, Co, Ni, TaN, Ta, or other refractory metal, orcombinations thereof.

FIGS. 8A-12C show exemplary sequential processes for manufacturing finstructures for an SRAM device according to one embodiment of the presentdisclosure. FIGS. 8A, 9A, . . . 12A are all the same figure illustratingthe fin structure layout in four adjacent SRAM unit cells subsequentlyformed. FIGS. 8B, 9B, . . . 12B show plan views in each manufacturingstage and FIGS. 8C, 9C, . . . 12C show cross sectional views along X1-X1or X2-X2 in FIGS. 8B, 9B, . . . 12B in each manufacturing stage. It isunderstood that additional operations may be provided before, during,and after processes shown by FIGS. 8A-12C, and some of the operationsdescribed below can be replaced or eliminated in additional embodimentsof the method.

FIG. 8A shows the fin structure layout in four adjacent SRAM unit cellssubsequently formed. The layout of the four SRAM unit cells is the sameas FIG. 4.

In one SRAM unit cell, for example, SR1, four fin structures 22, 24, 26and 28, which correspond to first to fourth fin structures of FIG. 2,respectively, are provided. The fin structures extend in the seconddirection (Y direction) and arranged in the first direction (Xdirection).

Within one cell, i.e., within one cell boundary, the first fin structure22 extends between a bottom side of the cell boundary and a top side ofthe cell boundary opposite to the bottom side. The second fin structure24 extends between the bottom side of the cell boundary and the top sideof the cell boundary opposite to the bottom side. The third finstructure 26 extends from the bottom side, and is shorter than the firstfin structure. The fourth fin structure 28 extends from the top side,and is shorter than the second fin structure. The first to fourth finstructures are arranged in the X direction with a predetermined space.The predetermined space is constant in this embodiment. The spacebetween the first and third fin structures may be different from thespace between the third and fourth fin structures.

The width of the fin structures is in a range from about 5 nm to about30 nm in some embodiments and is a range from about 7 nm to about 15 nmin other embodiments. The space Si between adjacent fin structures is ina range from about 20 nm to about 50 nm in some embodiments, and in arange from about 30 nm to about 40 nm in other embodiments.

As shown in FIGS. 8B and 8C, a first dummy pattern 110 is formed over asubstrate 10. The first dummy pattern 110 is made of inorganic materialssuch as silicon oxide and/or silicon nitride. A blanket layer of a firstmaterial is formed over the substrate 10 and then a patterning operationincluding a lithography operation and/or an etching operation isperformed to form the first dummy patterns 110.

When the first dummy pattern 110 is made of an inorganic material,chemical vapor deposition (CVD), physical vapor deposition (PVD) oratomic layer deposition (ALD) can be used to form the blanket layer.

The first dummy patterns 110 are formed in a line-and-pace shapeextending in the Y direction. The width of the first dummy pattern 110is substantially the same as space S2. As shown in FIGS. 8A and 8B, theleft edge the first dummy pattern 110 substantially corresponds to theright edge of the third fin structure 26 and the right edge of the firstdummy pattern 110 substantially corresponds to the left edge of thefourth fin structure 28. The first dummy patterns including dummypatterns 111, 112, 119, 114 and 117 extending in the Y direction areformed in this order in the X direction.

The thickness of the first dummy pattern 110 is in a range from about100 nm to about 300 nm.

Then, a blanket layer 120 of a second material is formed over the firstdummy patterns 110. The second material is an inorganic material such assilicon oxide and silicon nitride and is different from the firstmaterial. In this embodiment, silicon oxide formed by CVD is used. Thethickness of the second material from the upper surface of the substrate10 is in a range from about 5 nm to about 20 nm.

Since the thickness of the second material layer is sufficiently smallerthan the spaces 121, 123, 127 and 129 of the first dummy patterns, thesecond material layer does not fully fill the spaces and is conformallyformed over the first dummy patterns.

Next, anisotropic etching is performed on the blanket layer of thesecond material. As shown in FIGS. 9B and 9C, the second materialremains as sidewall spacers on the left and right sides of the firstdummy patterns, and after removing the first dummy patterns, maskpatterns 121B, 122A, 123A, 125B, 124A, 124B and 127A are formed.

The width of each of the mask patterns 121B, 122A, 123A, 125B, 124A,124B and 127A is substantially the same as or slightly larger than thewidth of the fin structures subsequently formed. The width is in a rangefrom about 7 nm to about 20 nm.

By adjusting the thickness and/or dimensions of the blanket layers offirst and second materials and the first dummy patterns, the desiredwidth and locations of the mask pattern can be obtained.

Next, as shown in FIGS. 10B and 10C, resist pattern 130 having openings135 is formed over the mask patterns. FIG. 10C is the cross sectionalview along line X2-X2 of FIG. 10B. Part of the mask patterns 122A and124B are exposed via the openings 135.

Then, the exposed portions of the mask patterns are removed by etchingoperations and the resist pattern 130 is removed. As shown in FIGS. 11Band 11C, the mask patterns 121B, 122A, 122B, 123A, 125B, 124A, 124B and127A corresponding to the fin structures to be formed remain on thesubstrate 10. The space between adjacent mask patterns within the cellboundary is constant in this embodiment.

By using the mask patterns 121B, 122A, 122B, 123A, 125B, 124A, 124B and127A as etching masks, trench etching is performed on the substrate 10,thereby forming fin structures 20, as shown in FIGS. 12B and 12C. Themask patterns are eventually removed.

FIGS. 13-17B show exemplary sequential processes for manufacturing gatestructures for an SRAM device according to one embodiment of the presentdisclosure. In FIG. 13, the SRAM unit cells having a 2-rows and3-columns arrangement is illustrated.

After the fin structures 20 are formed, an isolation insulating layer200 (see, FIG. 14B) is formed over the substrate so that upper portionsof the fin structures are exposed from the isolation insulating layer200. Then, blanket layers for a gate dielectric layer (not shown) and agate electrode layer 210 (see, FIG. 14B) are formed over the exposed finstructures and the isolation insulating layer 200.

Then, as shown in FIG. 13, second dummy patterns 220 are formed over thegate electrode layer 210. FIG. 13 is a top view (plan view) andunderlying fin structures 20 are shown in one of the SRAM unit cell forthe purpose of explaining relative locations of the fin structure andthe gate structures.

A blanket layer of a third material is formed over the gate electrodelayer and a patterning operation is performed to obtain the second dummypatterns 220 of the third material. The third material is one or morelayers of silicon oxide and/or silicon nitride.

In the patterning operation, design data having one thin rectangularpattern extending in the X direction within one SRAM unit cell areprepared and a photo mask having opaque patterns corresponding to thethin rectangular pattern is prepared (when a positive photo resist isused). In the present embodiment, the thin rectangular pattern isdisposed at the center line CL of the SRAM unit cell in the Y direction.In other words, on the photo mask (or the design data), only one patternis included in one SRAM unit cell. By using this photo mask, resistpatterns corresponding to the dummy patterns 220 are formed on theblanket layer of the third material, and the second dummy patterns 220are obtained by a dry etching operation.

After the second dummy patterns 220 are formed, a blanket layer of afourth material is formed over the second dummy patterns 220 and thegate electrode layer 210, and anisotropic etching is performed on thefourth material layer, thereby obtaining first hard mask layer 230 assidewall spacer layers, as shown in FIGS. 14A and 14B. FIG. 14A is a topview and FIG. 14B is a cross sectional view along the lines Y1-Y1 ofFIG. 14A.

Then, as shown in FIGS. 15A and 15B, the second dummy patterns 220 areremoved, thereby leaving the first hard mask patterns 230. FIG. 15A is atop view and FIG. 15B is a cross sectional view along the lines Y1-Y1 ofFIG. 15A. The width of the first hard mask pattern 230 at the bottomthereof is in a range from about 5 nm to about 15 nm.

As shown in FIG. 16, a patterning operation is performed to “cut” or“divide” the first hard mask patterns into plural pieces of first hardmask patterns 235 so as to correspond to the desired gate electrodepattern.

By using the “cut” first hard mask pattern 235, the gate electrode layer210 is patterned by dry etching into gate electrode pattern 215, asshown in FIGS. 17A and 17B. FIG. 17A is a top view and FIG. 17B is across sectional view along the lines X3-X3 of FIG. 17A. As shown in FIG.17B, the gate dielectric layer 217 is disposed over the exposed finstructures 20 and the gate electrode 215 is disposed over the gatedielectric layer 217.

If a gate replacement technology is used, the gate electrode 215 and thegate dielectric layer 217 are treated as dummy layers, which aresubsequently replaced with an actual gate electrode and a gatedielectric layer.

After the gate electrodes 215 are formed, portions of the fin structures20 not covered by the gate structure are recessed and source/drain (S/D)epitaxial layers 25 are formed in and above the recessed portions.

FIGS. 18-28B show exemplary sequential processes for manufacturingcontact bar structures for an SRAM device according to one embodiment ofthe present disclosure. In FIG. 18, the SRAM unit cells having a 2-rowsand 3-columns arrangement is illustrated.

After the gate structures and the S/D epitaxial layers are formed, aninterlayer dielectric layer (ILD) 250 is formed over the gate structuresand the S/D epitaxial layer. FIG. 18 is a cross sectional viewcorresponding to the line Y2-Y2 of FIG. 17A. Further, a blanket layer300 for a second hard mask layer is formed over the ILD layer 250, andfurthermore, a blanket layer 320 for a third dummy pattern is formedover the layer 300. The thickness of the ILD layer 250 is in a rangefrom about 20 nm to about 600 nm in some embodiments, and in a rangefrom about 50 nm to about 300 nm in other embodiments.

The ILD layer 250 is made of, for example, one or more layers of low-kdielectric material. Low-k dielectric materials have a k-value(dielectric constant) lower than about 4.0. Some low-k dielectricmaterials have a k-value lower than about 3.5 and may have a k-valuelower than about 2.5. The materials for the ILD layer 250 may includecompounds comprising Si, O, C and/or H, such as SiCOH and SiOC. Organicmaterial, such as polymers, may be used for the ILD layer 250. Forexample, the ILD layer 250 is made of one or more layers of acarbon-containing material, organo-silicate glass, a porogen-containingmaterial, and/or combinations thereof in certain embodiments. The ILDlayer 250 may be formed by using, for example, plasma-enhanced chemicalvapor deposition (PECVD), low pressure CVD (LPCVD), atomic layer CVD(ALCVD), and/or a spin-on technology.

The layer 300 for the second hard mask layer includes one or more layersof dielectric materials or metal material, such as TiN, poly-Si,amorphous Si, silicon oxide or silicon nitride. The thickness of eachlayer of the layer 300 is in a range from about 2 nm to about 200 nm insome embodiments, and in a range from about 5 nm to about 50 nm in otherembodiments.

The layer 330 for the third dummy layer includes one or more layers ofdielectric materials or metal material, such as TiN, poly-Si, amorphousSi, silicon oxide or silicon nitride. The thickness of each layer of thelayer 330 is in a range from about 2 nm to about 200 nm in someembodiments, and in a range from about 5 nm to about 50 nm in otherembodiments.

The layers 300, 320 and 330 may be formed by using, for example,physical vapor deposition (PVD), sputtering, plasma-enhanced chemicalvapor deposition (PECVD), low pressure CVD (LPCVD) and/or atomic layerCVD (ALCVD).

Then, as shown in FIG. 19, the third dummy patterns 325 are formed. FIG.19 is a top view (plan view) and underlying fin structures 20 and gateelectrodes 215 are shown in one of the SRAM unit cell for the purpose ofexplaining relative locations of the fin structure and the gatestructures. A patterning operation including lithography and dry etchingis performed to obtain the third dummy patterns 325.

In the patterning operation for the third dummy pattern 325, design datahaving one thin rectangular pattern extending in the X direction withinone SRAM unit cell are prepared and a photo mask having opaque patternscorresponding to the thin rectangular pattern is prepared (when apositive photo resist is used). In the present embodiment, the thinrectangular pattern is disposed in the bottom half of the SRAM unit cellin the Y direction. In other words, on the photo mask (or the designdata), only one pattern is included in one SRAM unit cell. By using thisphoto mask, resist patterns corresponding to the third dummy patterns325 are formed on the blanket layer 300, and the third dummy patterns325 are obtained by a dry etching operation.

After the third dummy patterns 325 are formed, a blanket layer of afifth material for a dummy hard mask layer is formed over the thirddummy patterns 325 and the ILD layer 250, and anisotropic etching isperformed on the fifth material layer, thereby obtaining second hardmask layer 330 as sidewall spacer layers, as shown in FIG. 20. Thethickness of the fifth material layer is in a range from about 2 nm toabout 70 nm in some embodiments.

Then, as shown in FIG. 21, the third dummy patterns 325 are removed,thereby leaving the dummy hard mask patterns 330 over the ILD layer 250.The width of the dummy hard mask pattern 330 at the bottom thereof inthe Y direction is in a range from about 2 nm to about 70 nm in someembodiments and is in a range from about 10 nm to about 40 nm in otherembodiments.

As shown in FIG. 21, the dummy hard mask patterns are formed on the cellboundary CELB in the X direction (top side and bottom side of the cellboundary) and inside each SRAM unit cell. In other words, each SRAM unitcell includes one dummy hard mask pattern having a full width and twodummy hard mask patterns having half of the full width.

As shown in FIGS. 22, 23A and 23B, a patterning operation is performedto “cut” or “divide” the dummy hard mask patterns 330 so as tocorrespond to the desired contact bar pattern.

A resist layer is formed over the second hard mask patters 330, and alithography operation is performed on the resist layer to form openings340, as shown in FIG. 22.

In the lithography operation, design data having opening patternssubstantially corresponding to the openings 360 are prepared and a photomask having transparent patterns corresponding to the opening patternsis prepared (when a positive photo resist is used).

Then, a dry etching operation is performed to cut (or divide) the dummyhard mask patterns 330 thereby forming “cut” dummy hard mask pattern(plural pieces of the dummy hard mask patterns) 335 as shown in FIGS.23A and 23B. FIG. 23B is a cross sectional view along line Y3-Y3 of FIG.23A. The shapes and locations of the “cut” dummy hard mask patterns 335substantially correspond to the contact bars that are subsequentlyformed.

Then, as shown in FIG. 24, a reversing layer 350 is formed over thelayer 330 and between the dummy hard mask patterns 335. The depositionprocess is designed to keep the top portion of the dummy hard maskpattern 335 exposed, as shown in FIG. 24. The reversing layer 350includes one or more layers of silicon oxide, silicon nitride, siliconcarbide (SiC), or SiON. Alternatively, the reversing layer 350 mayinclude polysilicon, photo resist, polymer, bottom anti-reflect coating(BARC), metals and other suitable materials. In the present embodiment,the material of the reversing layer 350 is chosen to withstand asubsequent etching process to remove the dummy hard mask pattern 335.The deposition of the reversing layer 350 is performed by techniques,such as CVD, PVD, spin-coating, epitaxially growth, thermal growth orother appropriated deposition techniques.

In order to expose the top portion of the dummy hard mask pattern 335,the deposition process may be a selective depositing process with asuitable thickness target. In the selective deposition process, thereversing layer 350 is formed on the layer 300 between the dummy hardmask patterns 335 but is not formed on the dummy hard mask patterns 335.And the thickness of the reversing layer 350 is controlled to ensure thetop portion of the dummy hard mask pattern 335 remain being exposed.Alternatively, a non-selective deposition process may be performed, suchas a spin-coating process. As an example, with a proper thickness targetof the spin-coating process, the top portion of the dummy hard maskpattern 335 may remain exposed. In the spin-coating process, thethickness of the spin-coating material may be controlled by severalfactors, such as spin-on material type and the spin speed.

Further alternatively, a non-selective and non-spin-coating depositionprocess may be performed to deposit the reversing layer 350 over thelayer 300 and the dummy hard mask pattern 335. An etch back process maybe applied to remove excessive the reversing layer 350 and expose thetop portion of the dummy hard mask pattern 335. As an example, achemical mechanical polishing (CMP) process is performed to remove aportion of reversing layer 350 such that the dummy hard mask pattern 335is exposed. In the depicted embodiment, the reversing layer 350 includespolysilicon, amorphous-Si, or a refractory metal formed by a depositiontechnique, such as CVD or PVD. An etch-back or a CMP process may beperformed thereafter to keep the top portion of the dummy hard maskpattern 335 exposed.

Next, as shown in FIGS. 25A and 25B, the dummy hard mask patterns 335are removed, thereby forming openings 360. FIG. 25A is a top view andFIG. 25B is a cross sectional view along line Y3-Y3 of FIG. 25A.

The dummy hard mask pattern 335 may be removed by dry etching, wetetching, or a combination thereof. An adequate etch selectivity of theremoving process minimizes loss of the sidewall of the reversing layer350, and results in a relatively vertical profile for the opening 360with substantially the same width as the removed dummy hard mask pattern335. The dimensions of the openings 360 substantially define thedimensions of the contact bars in a subsequent process.

Then, by using the reversing layer 350 with the openings 360 as anetching mask, the layer 300 is patterned into a third hard mask layer305 with openings 365, as shown in FIG. 26. The etching process may beanisotropic etching that forms a relatively vertical profile withsubstantially the same width/length as the opening 360, thereby leavingthird hard mask layer 305. Then, the reversing layer 350 is removed bydry etching and or wet etching.

Next, as shown in FIGS. 27A and 27B, the ILD layer 250 is etched byusing the third hard mask layer 305 as an etching mask, thereby formingvia holes/openings 375, which reach the S/D epitaxial layer 25.

After the formation of the via holes/openings 375, conductive materialincluding one or more of Cu, W, Al, AlCu, TiN, TiW, Ti, Co, Ni, TaN, Ta,or other refractory metal is filled in the via holes/openings 375. Aftera planarization operation, such as CMP, the contact bars 380 are formed,as shown in FIGS. 28A and 28B.

In the above embodiment, the layer 300 is formed over the ILD layer 250and is subsequently used as third hard mask layer 305. In otherembodiments, the layer 300 is not formed and the ILD layer 250 is etchedby using the reversing layer 350 with the openings 360 as an etchingmask.

The various embodiments or examples described herein offer severaladvantages over the existing art. For example, in the presentdisclosure, by using two photo masks in two photo lithographyoperations, gate electrode patterns and/or openings in the ILD layer forcontact bars with smaller dimensions can be uniformly formed.

It will be understood that not all advantages have been necessarilydiscussed herein, no particular advantage is required for allembodiments or examples, and other embodiments or examples may offerdifferent advantages.

In accordance with one aspect of the present disclosure, a method ofmanufacturing a static random access memory (SRAM) including a pluralityof SRAM cells, comprises the following operations. An insulating layeris formed over a substrate. First dummy patterns are formed over theinsulating layer. Sidewall spacer layers are formed, as second dummypatterns, on sidewalls of the first dummy patterns. The first dummypatterns are removed, thereby leaving the second dummy patterns over theinsulating layer. After removing the first dummy patterns, each of thesecond dummy patterns is divided into plural pieces of the second dummypatterns. A mask layer is formed over the insulating layer and betweenthe plural pieces of the second dummy patterns. After forming the masklayer, the plural pieces of the second dummy patterns are removed,thereby forming a hard mask layer having openings that correspond to theplural pieces of the second dummy patterns. The insulating layer ispatterned by using the hard mask layer as an etching mask, therebyforming via openings in the insulating layer. A conductive material isfilled in the via openings, thereby forming contact bars.

In accordance with another aspect of the present disclosure, a method ofmanufacturing a static random access memory (SRAM) including a pluralityof SRAM cells, comprises the following operations. An insulating layeris formed over a substrate. A first mask layer is formed over theinsulating layer. First dummy patterns are formed over the first masklayer. Sidewall spacer layers, as second dummy patterns, are formed onsidewalls of the first dummy patterns. The first dummy patterns areremoved, thereby leaving the second dummy patterns over the first masklayer. After removing the first dummy patterns, each of the second dummypatterns is divided into plural pieces of the second dummy patterns. Asecond mask layer is formed over the first mask layer and between theplural pieces of the second dummy patterns. After forming the secondmask layer, the plural pieces of the second dummy patterns are removed,thereby forming a first hard mask layer having openings that correspondto the plural pieces of the second dummy patterns. The first mask layeris patterned by using the first hard mask layer as an etching mask,thereby forming a second mask layer. The insulating layer is patternedby using the second hard mask layer as an etching mask, thereby formingvia openings in the insulating layer. A conductive material is filled inthe via openings, thereby forming contact bars.

In accordance with another aspect of the present disclosure, a method ofmanufacturing a static random access memory (SRAM) including a pluralityof SRAM cells, comprises the following operations. A first insulatinglayer is formed over a substrate. A first layer is formed over the firstinsulating layer. First dummy patterns are formed over the first layer.Sidewall spacer layers, as second dummy patterns, are formed onsidewalls of the first dummy patterns. The first dummy patterns areremoved, thereby leaving the second dummy patterns over the first masklayer. After removing the first dummy patterns, each of the second dummypatterns is divided into plural pieces of the second dummy patterns. Thefirst layer is patterned by using the plural pieces of the second dummypatterns as an etching mask, thereby forming gate patterns.

The foregoing outlines features of several embodiments or examples sothat those skilled in the art may better understand the aspects of thepresent disclosure. Those skilled in the art should appreciate that theymay readily use the present disclosure as a basis for designing ormodifying other processes and structures for carrying out the samepurposes and/or achieving the same advantages of the embodiments orexamples introduced herein. Those skilled in the art should also realizethat such equivalent constructions do not depart from the spirit andscope of the present disclosure, and that they may make various changes,substitutions, and alterations herein without departing from the spiritand scope of the present disclosure.

What is claimed is:
 1. A method of manufacturing a semiconductor device,the method comprising: forming source/drain epitaxial layers; forming afirst layer over the source/drain epitaxial layers, wherein the firstlayer includes a lower layer and an upper layer made of differentmaterial than the lower layer; forming a dummy pattern over the firstlayer, wherein the dummy pattern is formed of a metal material, TiN,polysilicon, amorphous silicon, silicon oxide, or silicon nitride;forming a second layer over the first layer and around the dummypattern; removing the dummy pattern, thereby forming a first opening inthe second layer; forming a via opening in the first layer by etchingthe upper layer through the first opening in the second layer, therebyforming a second opening; removing the second layer; and etching thelower layer through the second opening in the upper layer; and forming aconductive pattern by filling a conductive material in the via opening,thereby connecting adjacent source/drain epitaxial layers.
 2. The methodof claim 1, wherein the lower layer includes one or more layers ofSiCOH, SiOC, or an organic material.
 3. The method of claim 1, whereinthe upper layer includes one or more layers of TiN, poly-Si, amorphousSi, silicon oxide, or silicon nitride.
 4. The method of claim 1, whereinthe second layer includes one or more layers of silicon oxide, siliconnitride, silicon carbide (SiC), or SiON.
 5. The method of claim 1,wherein the second layer includes one or more layers of a photoresist, apolymer, or a bottom anti-reflective coating (BARC) material.
 6. Themethod of claim 1, wherein the second layer is formed such that a top ofthe dummy pattern is exposed.
 7. The method of claim 1, wherein thefirst layer and the second layer are formed of different materials.
 8. Amethod of manufacturing a semiconductor device, the method comprising:forming source/drain regions; forming one or more insulating layers overthe source/drain regions; forming a first pattern over the insulatinglayers, wherein the first pattern is formed of a metal material, TiN,poly silicon, amorphous silicon, silicon oxide, or silicon nitride;forming a second pattern over the insulating layers, the second patternhaving a reversed tone of the first pattern; patterning the one or moreinsulating layers by using the second pattern as an etching mask,thereby forming first and second openings; and forming a firstconductive pattern by filling a conductive material in the firstopening, and a second conductive pattern by filling the conductivematerial in the second opening, wherein: the semiconductor deviceincludes a static random access memory (SRAM), and the first conductivepattern connects a drain of a first pass-gate transistor, a drain offirst n-type transistor and a drain of first p-type transistor, and thesecond conductive pattern is connected to a source of the first passgate transistor or a source of the first n-type transistor.
 9. Themethod of claim 8, wherein the second pattern is made of differentmaterial than the first pattern.
 10. The method of claim 8, wherein theforming one or more insulating layers comprises forming a firstinsulating material layer over the source/drain regions, and forming asecond insulating material layer made of a different material than thefirst insulating material layer over the first insulating materiallayer.
 11. The method of claim 8, wherein the second pattern includesone or more layers of silicon oxide, silicon nitride, silicon carbide(SiC), or SiON, a photoresist, a polymer or a bottom anti-reflectivecoating (BARC) material.
 12. The method of claim 8, wherein the secondpattern includes one or more layers of silicon oxide, silicon nitride,silicon carbide (SiC), or SiON.
 13. The method of claim 8, wherein thesecond pattern includes one or more layers of a photoresist, a polymer,or a bottom anti-reflective coating (BARC) material.
 14. The method ofclaim 8, wherein the one or more insulating layers include one or morelayers of SiCOH, SiOC, or an organic material.
 15. A method ofmanufacturing a semiconductor device, the method comprising: formingsource/drain epitaxial layers; forming a first layer over thesource/drain epitaxial layers; forming a first dummy pattern and asecond dummy pattern over the first layer, wherein the first and seconddummy patterns are formed of a metal material, TiN, polysilicon,amorphous silicon, silicon oxide, or silicon nitride; forming a secondlayer over the first layer and around the first and second dummypatterns; removing the first and second dummy patterns, thereby forminga first opening and a second opening in the second layer; forming afirst via opening in the first layer and a second via opening by etchingthe first layer through the first opening and the second opening,respectively; and forming a first conductive pattern by filling aconductive material in the first via opening, thereby connectingadjacent source/drain epitaxial layers, and a second conductive patternby filling the conductive material in the second via opening, wherein:the semiconductor device includes a static random access memory (SRAM),and the first conductive pattern connects a drain of a first pass-gatetransistor, a drain of first n-type transistor and a drain of firstp-type transistor, and the second conductive pattern connects a drain ofa second pass-gate transistor, a drain of second n-type transistor and adrain of second p-type transistor.
 16. The method of claim 15, whereinthe first layer and the second layer are formed of different materials.17. The method of claim 15, wherein the first layer includes one or morelayers of SiCOH, SiOC, or an organic material.
 18. The method of claim15, wherein the first layer includes one or more layers of TiN, poly-Si,amorphous Si, silicon oxide, or silicon nitride.
 19. The method of claim15, wherein the second layer includes one or more layers of siliconoxide, silicon nitride, silicon carbide (SiC), or SiON.
 20. The methodof claim 15, wherein the second layer includes one or more layers of aphotoresist, a polymer, or a bottom anti-reflective coating (BARC)material.